The present invention is directed to a processor. More particularly, the present invention is directed to an interface to a memory system for a processor having a replay system.
The primary function of some processors is to execute computer instructions. Most processors execute instructions in the programmed order that they are received. However, some recent processors, such as the Pentium(copyright) II processor from Intel Corp., are xe2x80x9cout-of-orderxe2x80x9d processors.
An out-of-order processor can execute instructions in any order as the data and execution units required for each instruction becomes available. Some instructions in a computer system are dependent on one another because of their reference to particular registers (known as source dependency or register data dependency). Out-of-order processors attempt to exploit parallelism by actively looking for instructions whose input sources are available for computation, and scheduling them ahead of programmatically later instructions. This creates an opportunity for more efficient usage of machine resources and overall faster execution.
An out-of-order processor can also increase performance by reducing overall latency. This can be done by speculatively scheduling instructions while assuming that the memory subsystem used by the processor provides the correct data when the instruction is executed, as performed in the above-referenced parent application. However, several types of dependencies between instructions may inhibit the proper speculative execution of instructions. These dependencies may include register or source dependencies and memory dependencies. Addressing these dependencies increases the likelihood that a processor will correctly execute instructions.
Therefore, there is a need for a technique to adequately address the different types of dependencies that may prevent the proper execution of instructions in a processor.
According to an embodiment of the present invention, a computer processor is provided that includes a replay system for determining which instructions have not executed properly and replaying those instructions which have not executed properly. The processor also includes a memory execution unit coupled to the replay system for executing load and store instructions. The memory execution unit includes an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction so long as the invalid store flag is set.